There has been an increased demand for active safety systems for vehicles. Active safety systems require multiple radar sensors per vehicle, each radar sensor typically working with a specific radar technology. In an automotive application, the radar sensors are mostly built using a number of integrated circuits (ICs), sometimes referred to as ‘chips’. The current trend is towards offering a radar system on chip (SoC), using a radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) process technology) solution in order to reduce cost and power consumption. Commercial automotive radar sensors typically include multiple receivers and transmitters (the combination of which is referred to as transceivers (TRx)). A microcontroller (MCU) performs digital control of the transceiver circuits and digital signal processing of the digitized data (e.g. fast fourier transform (FFT) and digital signal processing) in order to output processed radar data to the MCU of the vehicle.
Next generation high performance radar solutions, used for highly automated or fully autonomous driving, will need to comply with stringent radar angular resolution requirements in both azimuth and elevation. Angular resolution is directly related to the radar system number of receiver antennas and their location with respect to each other. Current monolithic radar transceiver ICs are typically constrained to contain only a few transceiver channels, as the complexity and cost and heat dissipation problems of integrating more transceiver channels on the same chip increases substantially with the number of ICs that are included. To allow increased angular resolution in both azimuth and elevation, a multi-chip set solution with a master device and one or several slave devices may be used. With multi-chip set solutions, a master-slave (MS) clock signal is generated by the master device and used as a time base for synchronization of the microcontroller time based events with any other master device and all slave devices.
Duty cycle (DTC) monitoring circuits are well known in the literature, where they are typically coupled to a duty cycle corrector in order to track and correct a duty cycle of a given signal, generally a clock signal. In automotive radar applications that target safety-critical standards, such as ISO 26262, the use of duty cycle monitors is effectively mandatory, in order to guarantee signal integrity and provide a safety mechanism that is able to track any malfunctioning of a given circuit, such as a clock signal generator, or any circuit that uses clock signals. However, in modern Radar vehicle applications, for example applications that target highly-automated driving and further fully autonomous driving, the use of a DTC monitoring circuit coupled to a DTC corrector circuit is typically incompatible with the application. Effectively, a use of a ‘DTC corrector’ corrects the duty cycle failure, and by doing this, it hides the cause of the circuit or component failure, which is not ideal. Such a circuit or component failure, despite any duty cycle issue being corrected, may degrade a Radar system's performance (e.g. analog-to-digital conversion (ADC) performance, a signal-to-noise ratio (SNR) performance, a phase locked loop (PLL) performance, etc. This may lead to a mis-interpretation of the data processed by the Radar System. Indeed, for safety related applications, safety mechanisms such as very accurate and process-voltage-temperature (PVT)-insensitive DTC monitors are of high importance, and are used throughout a radar IC device, for both stand-alone transceiver, or multi-transceiver (cascading) radar applications.
In most DTC monitoring circuit implementations, a single-ended clock detector (or monitoring) circuit is used, thereby limiting the achievable DTC monitoring accuracy. DTC monitoring circuits that do not use single-ended clock detector circuits are typically very complex and use costly algorithms in order to increase DTC detection accuracy through a calibration process. Furthermore, known DTC monitoring circuits that use calibration circuits often require additional circuitry and storage, such as a look up table. This additional circuitry increases die area. Also, known DTC monitoring circuits often run in real-time, thereby increasing power consumption, in order to guarantee the DTC under temperature variations or fluctuations.
U.S. Pat. No. 8,773,186 B1 describes a DTC corrector circuit that includes a known DTC detector that is incapable of detecting fine differences in a generated signal duty cycle. In U.S. Pat. No. 8,773,186 B1, the duty cycle detector only provides information if the duty cycle is above or below 50%, and the feedback loop permanently adjusts the duty cycle (with the duty cycle corrector) around this 50% threshold. This approach results in a duty cycle that is 50% on average, but is permanently moving (e.g. maintained between 49%-51%). This type of behaviour is not good for most applications, as it can create a modulation on the clock signal duty cycle, which can create noise or spurious emissions (e.g. jitter) on the clock (ADC_clk in FIG. 1 of U.S. Pat. No. 8,773,186 B1 for example). Indeed, in this implementation, extensive calibration techniques must be used to improve the accuracy, thereby resulting in increased test time and additional circuitry for the calibration (additional die area).
Thus, a mechanism is needed to provide an improved duty cycle monitor circuit, for example one that operates within a broad, defined window of operation.